IEICE Trans. on Electronics. Vol. E77-C(7):1065-1074, 1994

A memory-based recurrent neural architecture
for chips emulating cortical visual processing.

Luigi Raffo
Istituto di Elettrotecnica- University of Cagliari, Piazza d'Armi, 09123 Cagliari, ITALY
Silvio P. Sabatini, Giacomo Indiveri, Giovanni Nateri and Giacomo M. Bisio
DIBE - University of Genoa, Via Opera Pia 11a, 16145 Genova, ITALY

The paper describes the architecture and the simulated performances of a
memory-based chip that emulates human cortical processing in early visual
tasks, such as texture segregation. The featural elements present in an image
are extracted by a convolution block and subsequently processed by the
cortical chip, whose neurons, organized into three layers, gain relational
descriptions (intelligent processing) through recurrent inhibitory/excitatory
interactions between both inter- and intra-layer parallel pathways.
The digital implementation of this architecture directly maps the set of
equations determining the status of the cortical network to achieve an
optimal exploitation of VLSI technology in neural computation.
Neurons are mapped into a memory matrix whose elements are updated
through a programmable computational unit that implements synaptic
By using 0.5um-CMOS technology, full cortical image processing can be
attained on a single chip (20x20 mm^2 die) at a rate higher than
70 frames/second, for images of 256x256 pixels.